1. Field of the Invention
The present invention relates generally to a high-speed programmable macrocell, and, more particularly, to such a macrocell having a combined signal path for storage and combinatorial modes.
2. Description of the Related Art
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions. Such a device consists of, generally, a group of programmable AND gates responsive to a plurality of inputs to generate predetermined product terms, a group of fixed/programmable OR gates responsive to the product terms for generating a plurality of sum-of-product (SOP) terms, and a macrocell responsive to the sum-of-product terms for generating a desired output. Sum-of-products terms can also be generated using programmable NOR-NOR logic.
In particular, such macrocell may be programmed to operate in a combinatorial mode, where its output follows its input, delayed by the propagation delay of the macrocell. The macrocell may be further programmed to operate in a storage mode, where its output is a function of a clock signal (i.e., the macrocell output is synchronous with the clock signal). Moreover, other features available in connection with the operation of the macrocell, and which may be programmable, include the output polarity of the macrocell (i.e., whether the output is active high, or active low). The macrocell may be programmed to operate in the combinatorial mode or the storage mode, the storage mode including a latch mode, and a registered mode. In the registered mode, the macrocell may be programmed to operate as a D-type flip-flop, or, a T-type flip-flop.
Referring now to FIG. 1, one approach in the prior art in the design of a macrocell for use in a programmable logic device is shown particularly as macrocell 10. Macrocell 10 includes functionality configuration 12, polarity configuration 14, a storage circuit 16, an inverter 18, a polarity multiplexer 20, an inverter 22, and a polarity multiplexer 24. Components 16, 18, and 20 define a storage path for input data to the output of macrocell 10, while components 22, and 24 define a combinatorial path through macrocell 10. Functionality configuration 12 includes such parameters as whether macrocell 10 operates in a combinatorial mode, in a registered mode (i.e., as a D-type, or a T-type flip-flop) or a latch during operation. Polarity configuration 14 determines whether the output of macrocell 10 will assume an active-high polarity, or an active-low polarity. Configuration blocks 12, and 14 may take the form of a bit value for each parameter.
FIG. 2 shows the conventional macrocell 10 of FIG. 1 in greater detail. The storage path referred to above includes the following components, whose operation will be described below: polarity multiplexer 20 (shown enclosed by a dashed-line box), a first OR-AND-INVERT complex gate 26, inverter 28, transmission gate 30, transmission gate 32, a second OR-AND-INVERT complex gate 34, inverter 36, and transmission gate 38. Polarity multiplexer 20 includes transmission gate 39, and tristate inverting buffer 40. A master circuit is formed by multiplexer 20, and components 26, 28, and 30. A slave circuit is formed by components 32, 34, 36, and 38. The output portion of the storage path is defined by tristate inverting buffers 42, 44, 46, and 48.
The combinatorial path is defined by inverters 22a and 22b, and polarity multiplexer 24a, and polarity multiplexer 24b. Multiplexer portions 24a and 24b, together, form polarity multiplexer 24, as shown in FIG. 1. Polarity multiplexer 24a includes tristate inverting buffers 50 and 52, while multiplexer 24b includes tristate inverting buffers 54, and 56. Logic 57 ensures that buffers 50, 52, 54, and 56 operate only the combinatorial mode. The tristate inverting buffers may take the simplified form as shown in FIG. 3, which includes a pair of PMOS transistors 58, and a pair of NMOS transistors 59 connected in series, with the middle node being the output. Operation of the tristate inverting buffer should be apparent to one of ordinary skill in the art from the foregoing description, accompanied by FIG. 3.
During operation, it should be observed that two output signals, data.sub.-- out, and data.sub.-- outb (i.e. b=bar, or complement), are used in macrocell 10 in order to drive an output buffer coupled to macrocell 10. Polarity configuration bit 14 is used to select the desired output polarity of macrocell 10. Inverters 22a, and 22b are used to generate an opposite phase of the input data.sub.-- in. With the combinatorial input bit set so as to select the combinatorial mode, one of tristate inverters 50, and 52, and one of tristate inverters 54, and 56 are conducting, while tristate inverters 42, 44, 46, and 48 are not conducting, and are thus in a high-impedance state.
When macrocell 10 is set to operate in the storage mode of operation, particularly the registered mode, tristate buffers 50, 52, 54, and 56 are always nonconducting. Polarity multiplexer 20 (part of the master circuit) for the registered path is implemented separately from the polarity multiplexer for the combinatorial path, which uses transmission gate 39, and tristate buffer 40. When an input clock signal is in a low state, only one of gates 39 and 40 will conduct, depending on the selected output polarity. At this time (when clock is low) gates 44, 38, and 46 will conduct while gates 42, 30, 32, and 48 will not conduct. Gate 29 is also off.
When the input clock signal transitions to a high state, gates 44, the previously conducting one of gates 39 and 40, 38 and 46 will not conduct, while gates 42, 30, 32, and 48 will conduct. Input data held in the master circuit is stored in the slave circuit and now appear as data.sub.-- out, and data.sub.-- outb. The set and reset functions of macrocell 10 are implemented using OR-AND-INVERT complex gates 26, and 34 and set/reset logic. The complex gates operate as follows: when either of the in, or set inputs of the OR-AND-INVERT gate are high, and reset (to the macrocell 10) is low, the outb of the gate is low. When the reset signal is high, the outb output of the gate is high.
One major disadvantage of the conventional macrocell 10 is the large area used by the macrocell, due in large part to the use of separate output polarity muxes for each of the storage, and combinatorial paths, and further, due to the large number of tristate inverting buffers. Moreover, macrocell 10 suffers from a speed penalty for the T.sub.co (clock-to-part-to-output delay), and T.sub.pd (propagation delay in combinatorial mode) parameters because of self loading on the data.sub.-- out and data.sub.-- outb nodes. Moreover, the so-called set-up time T.sub.s parameter for the registered mode suffers due to the set-reset complex gates used for performing the set-reset functions. Finally, the conventional macrocell 10 also has a potential speed penalty for the T.sub.pd, and T.sub.s parameters because of loading on the data.sub.-- in node.
Accordingly, there is a need to provide an improved macrocell structure for use in programmable logic devices (PLDs) that minimizes or eliminates one or more of the problems as set forth above.